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GET READY FOR TAPE OUT

LAYR is the challenge for the next generation of chip designers.

YOUR GATEWAY TO CHIPDESIGN

New contacts. New skills. Real chips.

Whether you are just getting started in chip design or already have some experience, at LAYR you will work in a team on real projects and see how ideas turn into real chips. You will gain practical experience, earn ECTS credits, and contribute your expertise to the open-source community.

From the initial concept to the finished silicon: using modern open-source technologies, you will develop your own chip design step by step. Mentors, development boards, and a professional toolchain will support you along the way. All submitted designs will be manufactured—so you'll end up holding your own chip in your hands.

DESIGN TEACHING WITH LAYR

Experience open source. Teach in a practical way. Pass on knowledge.

From theory to practice: The LAYR competition can be flexibly integrated as a series of seminars, in project work or as elective modules without additional effort. The didactically prepared open educational materials, tutorials and ‘Teach-the-Teacher’ videos are available free of charge and can be adapted.

Promote talent and strengthen innovation.

Give fresh impulses. Promote young talent. Shape the future.

 

 

In cooperation with universities, industry, research institutions and the open source community, practical learning spaces are created in which students work on real-world challenges. This not only generates new ideas, but also fosters valuable connections between science, business and young talent. As a LAYR partner, you promote talent, research and open innovation and play an active role in training future specialists.

News

Latest announcements

Open-source technologies are becoming more and more important in chip design, opening up new possibilities for education, research, and collaboration.…
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On 6th and 7th of May, the German chip design community gathered in Dresden for the Chipdesign Germany Forum. Alongside technical deep dives,…
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First Challenge Prototype: “Security by Design” How can security be embedded directly into the design of modern chips? With the first Open Source…
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Open hardware stands for transparency, participation and digital sovereignty. But how can these values be realised in a student competition, from the…
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The Challenge

The challenge of the competition calls for creativity and team spirit and builds solid expertise in open-source chip design. Over several rounds, the teams tackle a central task that becomes more demanding with each level. Each level has its own objectives, learning materials and technical mentoring support from experts in research and industry.

Trial Run 2025

The trial run of the LAYR Challenge 2025 ‘Security by Design’ is currently running with three university teams. The next official run will start in the summer semester of 2027.

Level 0

Your chip does not contain any additional countermeasures, but the functional correctness of the simple LAYR identification protocol must be ensured. In addition, a basic form of threat modelling should be carried out and documented.

Level 1

Instead of simply reading a static ID, the improved LAYR authentication protocol (see protocol specification) must be implemented. Here too, functional correctness must be ensured.

Level 2

Protection against passive (power) side-channel attacks – You are free to choose which types of countermeasures (masking, concealment, etc.) to implement and to what extent. All steps must be fully documented and justified. The considerations should be presented in such a way that it is clear why certain countermeasures were chosen and what effect they are intended to have.

Level 3

Freely selectable countermeasures (e.g. temporal redundancy, spatial redundancy, information redundancy) can also be implemented at this stage. The decisions made must be documented in a comprehensible manner.

LAYR - Newsletter

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