Assistant Professor for reconfigurable Computerarchitectures at Graz University of Technology, RISC-V-Advocate
Tobias Scheipel is an Assistant Professor of Reconfigurable Computer Architectures at the Institute of Computer Engineering at Graz University of Technology and a RISC-V Advocate. He completed his PhD under the supervision of Prof. Marcel Baunach and was awarded a Doctor of Engineering (Dr.techn.) sub auspiciis Praesidentis. His research focuses on sustainable, flexible and runtime-reconfigurable microcontroller architectures for embedded systems – in particular FPGA-based RISC-V – at the interface between hardware and software, including processor logic and operating systems.
What is your take on open-source chip design as a turning point?
>> Transparency is becoming the norm, not a privilege! No more reverse engineering, no more expensive, vendor-locked tools, no more extremely high barriers to entry! When the RTL, test infrastructure and documentation are open, you don’t have to guess what the hardware does; you can examine, simulate and validate it. This shifts trust from ‘because the vendor says so’ to ‘because we can verify it’ <<